Advanced Compiler Construction

Mössenböck 2KV Tu 13:45 - 15:15 MT127 Start: 05.03.2019

This course continues the course "Übersetzerbau" (Compiler Construction) in the Bachelor's program. It concentrates on code generation for register machines as well as on compiler optimizations based on intermediate program representations. The lectures will only run until the beginning of June. The rest of the semester is reserved for a project in which you will build a small compiler for a register machine using the compiler generator Coco/R.

Prerequisite: Übersetzerbau (or a similar compiler construction course)

Note that Advanced Compiler Construction will be offered only every second year.


  1. Symbol table and separate compilation
    - Recap: objects, types, scopes
    - Separate compilation in a Pascal-like language
    - Separate compilation in Java

  2. Code generation for register machines
    - Intel IA-32 architecture
    - Design considerations
    - Code buffer management
    - Register allocation
    - Operands during code generation
    - Emitting machine instructions
    - Loading values and addresses
    - Code generation for expressions
    - Code generation for statements
    - Jumps
    - Code generation for control structures
    - Short-circuit evaluation of boolean expressions
    - Code generation for procedures
    - Contents of the object file

  3. Intermediate representations
    - Abstract syntax tree
    - Control-flow graph
    - Def-Use information
    - Dominator tree
    - Static Single Assignment Form (SSA form)

  4. Optimizations
    - Motivation
    - Simple optimizations
    - Copy Propagation
    - Common Subexpression Elimination
    - Dead Code Elimination
    - Procedure optimizations
    - Loop optimizations
    - Instruction Scheduling
    - Peephole optimization

  5. Register allocation
    - Simple register management
    - Register variables
    - Graph Coloring
    - Elimination of Phi instructions
    - Saving and restoring registers


Date Time Room Topic
Tu 05.03 13:45 - 15:15 MT127 Symbol Table
Tu 12.03. -- no lecture --
Tu 19.03. 13:45 - 15:15 MT127 Code Generation
Tu 26.03. 13:45 - 15:15 MT127 Code Generation
Tu 02.04. 13:45 - 15:15 MT127 Code Generation
Tu 09.04. 13:45 - 15:15 MT127 Intermediate Representations
Tu 30.04. 13:45 - 15:15 MT127 Intermediate Representations
Tu 07.05. 13:45 - 15:15 MT127 Optimizations
Tu 14.05. -- no lecture --
Tu 21.05. 13:45 - 15:15 MT127 Optimizations
Tu 28.05. 13:45 - 15:15 MT127 Register Allocation
Tu 04.06. -- no lecture --
Tu 02.07.
13:45 - 15:15


The slide copies as well as other material can be downloaded from the Kusss page of this course.


  • Aho A.V., Lam M.: Compilers -- Principles, Techniques and Tools. 2nd edition, Addison Wesley, 2006
  • Cooper, K.D., Torczon, L.: Engineering a Compiler. 2nd edition, Morgan Kaufmann, 2012
  • Appel A. W.: Modern Compiler Implementation in Java. 2nd edition, Addison-Wesley, 2002
  • Muchnick, S.: Advanced Compiler Design and Implementation. Morgan Kaufmann, 2003
  • Wirth N.: Grundlagen und Techniken des Compilerbaus. Oldenbourg, 2008


There will be a written exam on Tuesday, July 2, 2019, 13:45-15:15 (without handouts). You should also do one of the projects described below.


Since this is a combined course (KV) you should also do one of the following 2 projects in addition to the exam. The project is not mandatory. However, without the project, the best mark you can achieve is a 2 (gut). If you submit a correct project and if you have at least 40 out of 90 points in the exam your exam mark will be automatically raised by 1.

  • Project 1: Code Generation for a Register Machine
    Develop a compiler for a small programming language generating code for the Intel IA32 architecture. No intermediate representation is to be built. Also, register allocation should be done on the fly, i.e., without graph coloring.

  • Project 2: Compiler Optimizations on an IR
    Develop a compiler for a small programming language building an intermediate representation of the source program (CFG with instructions in SSA form) and performing certain optimizations on it. Optionally you can also implement a register allocator. Code generation is not required.

The project should be handed in on Tuesday, July 2, 2019 between 15:30 and 17:30. Please come with your notebook to the lecturer's office and present your project. If you cannot finish your project until then, there will be a second submission opportunity on Friday, October 4, 2019 between 13:00 and 14:00.

In both projects, the scanner and the parser are to be generated with the compiler generator Coco/R so that you can concentrate on other tasks.

For implementing the code generator you need a detailed specification of the IA32 architecture and its instruction encoding. You can find it here:

In order to load and run the code generated by your compiler (Project 1) you should use the following mini loader (source, executable) as described in the project specification. If you compile the loader with Visual Studio you can use Visual Studio to inspect and debug the generated binary code.